Hardware Accelerator Design of DCT Algorithm With Unique-Group Cosine Coefficients for Mel-Scale Frequency Cepstral Coefficients

This study presents a compact L-points discrete cosine transform (DCT) hardware accelerator for M-points Mel-scale Frequency Cepstral Coefficients (MFCC). The main contributions of this work can be summarized as 1) proposing an algorithm with lower complexity; 2) achieving higher accuracy performance; 3) implementing low-cost unique group coefficients. For derivation, the proposed method converts original formula into type IV (DCT-IV) preprocessing procedure. kernel computation DCT-IV further derived same multiplication preprocessing. Therefore, total (M-1) (L-1) additions, L multiplications, and coefficients are required computation. Compared Jo et al.’s algorithm, respectively reduces number additions multiplications by 42.32 % 41.67 %. Instead, is increased 33.33 Moreover, exhibits peak signal-to-noise ratio (PSNR) value which achieved at 90.1dB 16-bit coefficient word length. realization, FPGA implementation results show that it operate clock rate 135.85 MHz requires only 113 combinational elements, 87 registers, 3 DSP multipliers, 64×16 bits RAM 32×16 ROM. Overall, would good choice integrating MFCC applications in future.